What’s New: Intel’s Programmable Solutions Group today announced that the Intel Agilex® 7 with the R-Tile chiplet is shipping production-qualified devices in volume – bringing customers the first FPGA with PCIe 5.0 and CXL capabilities and the only FPGA with hard intellectual property (IP) supporting these interfaces.
“Customers are demanding cutting-edge technology that offers the scalability and customization needed to not only efficiently manage current workloads, but also pivot capabilities and functions as their needs evolve. Our Agilex products offer the programmable innovation with the speed, power and capabilities our customers need while providing flexibility and resilience for the future. For example, customers are leveraging R-Tile, with PCIe Gen 5 and CXL, to accelerate software and data analytics, cutting the processing time from hours to minutes.”
–Shannon Poulin, Intel corporate vice president and general manager of the Programmable Solutions Group
Why It Matters: Faced with time, budget and power constraints, organizations across industries including data center, telecommunications and financial services, turn to FPGAs as flexible, programmable and efficient solutions. Using Agilex 7 with R-Tile, customers can seamlessly connect their FPGAs with processors, such as 4th Gen Intel® Xeon® Scalable processors, with the highest bandwidth processor interfaces to accelerate targeted data center and high performance computing (HPC) workloads. Agilex 7’s configurable and scalable architecture enables customers to quickly deploy customized technology – at scale with hardware speeds based on their specific needs – to reduce overall design costs and development processes and to expedite execution to achieve optimal data center performance.
How It Works: Agilex 7 FPGAs with the R-Tile chiplet deliver leading technology capabilities with 2-times faster PCIe 5.0 bandwidth as well as 4-times higher CXL bandwidth per port when compared to other competitive FPGA products. According to a white paper from Meta and the University of Michigan, adding FPGAs with CXL memory to 4th Gen Xeon-based servers while using transparent page placement’s (TPP) efficient page placement improves Linux performance by up to 18%. Additionally, UnifabriX demonstrated its CXL-enabled Smart Memory Node on multiple performance benchmarks, with one showing a 28% increase in the HPCG (high-performance conjugate gradient) benchmark score while utilizing 2-times more 4th Gen Xeon cores for HPC workloads.