Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows have been certified to support TSMC’s new Design Rule Manual (DRM) for the foundry’s advanced N3E and N2 nodes. The companies also delivered N3E and N2 process design kits (PDKs) to facilitate mobile, AI and hyperscale computing IC design innovation at these nodes. Customers are actively using these new nodes and certified Cadence® flows to achieve power, performance and area (PPA) goals, simplify analog migration and speed time to market.
N3E and N2 Digital Full-Flow Certification
Cadence collaborated with TSMC on its complete RTL-to-GDS flow for use with TSMC’s N3E and N2 nodes includes the Innovus™ Implementation System, Quantus™ Extraction Solution and QuantusField Solver, Tempus™ Timing Signoff Solution and ECO Option, Pegasus™ Verification System, Liberate™ Characterization Portfolio, Voltus™ IC Power Integrity Solution, and Voltus-Fi Custom Power Integrity Solution. The Genus™ Synthesis Solution with predictive iSpatial technology is also enabled for the latest N3E and N2 technologies.
The full Cadence digital implementation and signoff flow supports a variety of new design features, including native hybrid cell row optimization from synthesis to signoff ECO for optimal PPA at N3E, cell pin alignment and connection support. The flow is ready for customers to adopt rapidly so they can experience the benefits associated with the latest TSMC N3E and N2 process technologies.
N3E and N2 Custom/Analog Flow Certification
The Cadence Virtuoso® Studio, including the Virtuoso Schematic Editor, Virtuoso ADE Suite and Virtuoso Layout Suite as well as the Spectre® Simulation Platform, including Spectre X Simulator, Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS) and the Spectre RF Option, are optimized for managing corner simulations, statistical analyses, design centering, and circuit optimization. The latest Virtuoso ADE Suite architecture helps users optimize their designs by running up to thousands of simulation points in parallel on modern compute farms or in a public or private cloud.
The Virtuoso Layout Suite includes multiple innovations that deliver a more efficient IC layout including better performance and scalability; grid-based structured device placement methodology with interactive, assisted features for placement, routing, fill and dummy insertion; a new device-level auto router designed to address advanced-process node challenges; enhanced analog migration and layout reuse functionality to port custom design and layout across the latest TSMC advanced process nodes; integrated parasitic extraction and EM-IR checks; and integrated signoff-quality physical verification capabilities using the Pegasus Verification Solution.
“It’s vital that our customers have access to design tools that are certified for use with our most advanced N3E and N2 processes, so they can benefit from the significant power and performance improvements of our latest technology innovations,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “By continuing to collaborate with Cadence, we’re always finding new ways to deliver value to our customers who work every day to bring next-generation silicon innovations to life.”
“Both Cadence and TSMC are committed to making technology advancements that shape the future of electronic design and enable engineers to reach PPA and productivity goals,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “As the demand for chips continues to rise, the pace of innovation must follow, and we’re confident that our customers can achieve design success using our digital and custom/analog design flows coupled with TSMC’s N3E and N2 technologies.”
The Cadence digital and custom/analog flows support the Cadence Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence. To learn more about Cadence’s advanced-node solutions, visit www.cadence.com/go/advndn3en2.